The present invention generally relates to a computer system in which a single memory system or a single storage is shared by a plurality of processing elements such as vector processors. More particularly, the invention is concerned with a computer system in which an access conflict arbitration scheme is adopted for preventing access performance of a main storage from being degraded when an access instruction issued to the main storage includes a plurality of access requests.
There are known several arbitration schemes for priority circuits adapted for selecting one or some from a plurality of access requests. For example, there are known an arbitration schemes in which access requests are selected in accordance with priorities allocated fixedly to the requests, in which requests are selected orderly, starting from the oldest one, in which a request is selected at random from plural ones, and in which a request not selected is newly allocated with a higher priority (disclosed in JP-A-63-66662) and so forth.
A system in which access conflict taking place when a plurality of requesters issue access requests to a plurality of storages is solved by resorting to an arbitration scheme such as mentioned above is disclosed in JP-A-63-66662. This system will first be described by reference to FIG. 17.
In the figure, reference numerals 151, 152, 153 and 154 denote requesters (REQ) which issue access requests to a main storage 168, a numeral 159 denotes a storage control unit (SCU) for sending the requests to the main storage 168 by arbitrating conflict or competition among the requests sent from the requesters (REQ), and a numeral 173 denotes a fetched data buffer for rearraying data read or fetched from the main storage 168 in the order in which the requests were issued by the requesters 151 (REQ0), 152 (REQ1), 153 (REQ2) and 154 (REQ3).
The requesters 151, 152, 153 and 154 are incorporated in associated vector processors (not shown), respectively, and include request senders 155, 156, 157 and 158, respectively, for sending out the requests.
The storage control unit 159 is comprised of request queues 160 (labeled QUE0), 161 (QUE1), 162 (QUE2) and 163 (QUE3) and priority circuits 164 (PR0), 165 (PR1), 166 (PR2) and 167 (PR3) for determining the priority to thereby select the request which is to be first processed upon occurrence of conflict between or among the requests.
The main storage 168 is comprised of four bank groups (memory modules) 169 (labeled BG0), 170 (BG1), 171 (BG2) and 172 (BG3), wherein the bank group or memory module BG0 includes a plurality of memory banks BK0 TO BK3, while the bank group BG1 includes memory banks BK4 to BK7 with the bank group BG2 including memory banks BK8 to BK11 and the bank group BK3 including memory banks BK12 to BK15. The time taken for one requester to make access to the memory bank amounts to several clocks. This time will be referred to as the memory access time. In case any one of the memory banks is being accessed by one of the requests, the other requests are inhibited from accessing that one memory bank.
Concerning the structure of the fetched data buffer 173 in detail, reference may have to be made to JP-A-60-136849, the disclosure of which is herein incorporated by reference.
Next, referring to FIG. 21, a configuration of the priority circuit will be described in detail by taking as example the priority circuit 164.
In FIG. 21, reference numerals 208, 209, 210 and 211 denote registers for holding priority bits of the associated requesters, respectively, numerals 200, 201, 202 and 203 denote set/reset logic, respectively, 213 denotes a priority logic, 212 denotes an OR circuit, 214 denotes a decoder, and a numeral 215 denotes a request register. In the priority circuit 164, the requests issued by the requesters 151 to 154 (FIG. 17) are once latched by request buffer registers 204, 205, 206 and 207, respectively, and selected by the priority logic 213 in accordance with the priority information bits held by the priority bit registers 208, 209, 210 and 211, respectively, wherein the access request as selected is held by the request register 215. At the same time, the request buffer registers 204, 205, 206 and 207 inform the set/reset circuits 200, 201, 202 and 203 of the requests being issued, respectively. The priority logic 213 issues an identification (ID) number of the vector processor to which the requester issued the selected request belongs. This ID information of the vector processor is decoded by the decoder 214 and be sent to one of the set/reset circuits 200, 201, 202 and 203 which corresponds to the vector processor indicated by the decoded ID. On the other hand, the values placed in the priority bit registers 208, 209, 210 and 211 are sent to the set/reset circuits 200, 201, 202 and 203, respectively, after having been logically ORed by the OR circuit 212.
Next, description will turn to a method of setting/resetting the priority bit register 208, 209, 210 or 211 by the corresponding set/reset circuit 200, 201, 202 or 203.
The priority bit register 208, 29, 210 or 211 is set, provided that the request is present in the associated request register 204, 205, 206 or 207, the signal delivered from the decoder 214 is "0" indicating that the above-mentioned request is not selected by the priority logic 213, and that the output value of the OR circuit 212 is "0" indicating that none of the priority bit registers is set.
The priority bit register is reset when the signal outputted from the decoder 214 is "1", i.e., when the request held by the associated requester is selected by the priority logic 213.
Next, description will be directed to the request processing flow.
Referring to FIG. 17, the requesters 151 (REQ0), 152 (REQ1), 153 (REQ2) and 154 (REQ3)are designated to issue the respective requests each having a bank group ID number, a bank ID number and an intrabank address for the destination. The requests as issued are temporarily held by the request queues QUE0, QUE1, QUE2 and QUE3 which correspond to the above-mentioned requesters, respectively, and which are incorporated in the storage control unit 159.
In the state in which the requests are held by the request queues QUE0, QUE1, QUE2 and QUE3, the bank group ID numbers of the requests held in these queues are discriminatively identified to thereby allow the requests to partake in the conflict arbitrations effected by the priority circuits 164 (PR0), 165 (PR1), 166 (PR2) and 167 (PR3) which are provided in correspondence to the bank groups 169, 170, 171 and 172, respectively.
Each of the priority circuits PR0, PR1, PR2 or PR3 selects the request which partakes in the conflict arbitration and which has the priority bit of "1", whereby one of the selected requests is outputted. In case none of the requests having the respective priority bits of "1" exists, one request is selected from all the requests partaking in the conflict arbitration, and subsequently the priority bits of the requests not selected are all set to "1", respectively. Since the priority bits are managed by the respective priority circuits independent of one another, the priority may differ from one to another priority circuit.
By way of example, let's consider the request selected by the priority circuit PR0. This request is sent to one of the memory banks BK0, BK1, BK2 and BK3 belonging to the bank group BG0 in accordance with the destination memory bank ID number added to the selected request. Same holds true for the priority circuits PR1, PR2 and PR3.
In case the instructions being executed by the vector processors are load instructions, data read out from the respective memory banks after lapse of the memory access time (which is assumed to correspond to four clocks in this case) are rearrayed in the fetched data buffer 173 in the order in which the corresponding requests were issued, whereon the data are sent to the respective requesters. On the other hand, when the instructions as executed are store instructions, data (as resulted from the execution are written in the corresponding memory banks, whereupon the access processing comes to an end.
As will be understood from the above, according to the conflict arbitration technique known heretofore, the priority circuits determine the priorities of the requests independent of one another so as to prevent any given one of the requests from being forced to wait for processing for a long time.
The inventors have however found that the system shown in FIG. 17 and described above suffers problems mentioned below when the requesters issue the requests for the instructions which differ from one another.
More specifically, let's assume that instructions A and B are issued simultaneously by the requesters REQ0 and REQ1, respectively, wherein the instructions A and B include request sets {a.sub.0, a.sub.1, a.sub.2, a.sub.3 } and {b.sub.0, b.sub.1, b.sub.2, b.sub.3 }, respectively, and that the memory banks BK0, BK4, BK8 and BK12 are to be accessed sequentially in this order for executing the instructions A and B.
FIG. 18 illustrates in a time chart the processing of requests mentioned above.
Referring to FIG. 18 along with FIG. 17, the requesters 151 (REQ0) and 152 (REQ1) issue sequentially access requests for the instructions A and B, respectively. The access requests are held by the request queues at a succeeding clock generated by the requesters REQ0 and REQ1 and at the same time undergo the conflict arbitration effected by the priority circuits PR0, PR1, PR2 and PR3.
In this case, the requests a.sub.0 and b.sub.0 conflict with each other in the priority circuit PR0, the requests a.sub.1 and b.sub.1 conflict each other in the priority circuit PR1, the requests a.sub.2 and b.sub.2 conflict in the priority circuit PR2, and the requests a.sub.3 and b.sub.3 conflict each other in the priority circuit PR3. It is now assumed that in the priority circuits PR0, PR2 and PR3, the priority bit of the requester REQ0 is "1" with the priority bits of the requesters REQ1, REQ2 and REQ3 being "0", respectively, while in the priority circuit PR1, the priority bit of the requester REQ1 is "1" with those of the requesters REQ0, REQ2 and REQ3 being "0". There, the requests a.sub.0, b.sub.1, a.sub.2 and a.sub.3 are selected in the priority circuits PR0, PR1, PR2 and PR3, respectively.
The requests a.sub.0, b.sub.1, a.sub.2 and a.sub.3 as selected are sent to the memory banks BK0, BK4, BK8 and BK12 of the bank groups BG0, BG1, BG2 and BG3, respectively, at a succeeding clock. From these memory banks accessed by the above-mentioned requests, data are read out after time lapse corresponding to four clocks to be thereby transferred to the fetched data buffer 173.
The memory banks accessed by the requests are inhibited from being accessed for the memory access time corresponding to the four clocks. Consequently, the requests b.sub.0, a.sub.1 , b.sub.2 and b.sub.3 remaining unselected can partake in the conflict arbitration only after completion of the access request processing for the selected requests a.sub.0, b.sub.1, a.sub.2 and a.sub.3.
In the fetched data buffer 173, a set of data as read out from the memory banks are rearrayed in the order in which the corresponding requests were issued and then sent to the requesters issued these requests. Consequently, even a delay in reading the data constituting a member of the data set mentioned above will prohibit the sending of the other data to the concerned requesters. In the case of the example now under consideration, the access request a.sub.1 of the instruction A is processed with a delay of four clocks while the requests b.sub.0, b.sub.2 and b.sub.3 of the instruction B are processed with a delay of four clocks, respectively, involving a delay of four clocks in sending the data to the requester REQ0 and REQ1. Thus, executions of the instructions A and B are both delayed by four clocks, respectively.
In this conjunction, it will be noted that when the request a.sub.1 of the instruction A is allocated with higher priority than the request b.sub.1 for the instruction B, no delay takes place in the processing of the instruction A. In other words, execution of the instruction A can be completed without any delay.
As is apparent from the above discussion, in the circuit configuration in which one set of requests is outputted from each of the requesters to a plurality of priority circuits and in which the priority circuits manage the priorities of the requests independent of one another and change the priorities upon every selection of the requests, occurrence of conflict between or among the requests belonging to the different sets may provide a cause for delay in the processing of the requests of both sets.
In a multiprocessor system operating in a computer center or the like, there may arise a situation in which a particular one of the processors is imparted with a high priority for execution of the processing allocated thereto. In that case, in order to prevent the system performance from degradation due to the conflict with the main storage access instruction(s) for the other processor(s), it becomes necessary to allocate a higher priority to the main storage access request of the particular processor.